The development and fabrication of advanced integrated circuits typically employs layout software, which displays the layout of the chip. Non-limiting examples include packages available from Mentor Graphics, Wilsonville, Oreg., USA; XYALIS, Grenoble, France; and Cadence Design Systems, Inc., San Jose, Calif., USA. Test, diagnostics, and failure analysis of ICs may employ various analytical tools. Non-limiting examples include emission-based techniques, laser voltage probes, laser stimulation tools, focused ion beams (FIB), and the like.
U.S. Pat. No. 6,185,707 of Smith et al. discloses an IC test software system for mapping logical functional test data of logic integrated circuits to a physical representation. The system of the Smith et al. patent determines and displays the X, Y location corresponding to a net name, by translating functional test data of a digital logic chip passed through a simulation model which identifies one or more defective nets of the chip. The defective nets are processed against a database to obtain X, Y coordinate data for these nets, allowing them to be data logged as physical traces on the chip layout.